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By David Williamson, Shaffer Kurt R, Squire Richard Halverson, James P. Gee

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Again a reduction of the design space is achieved. Typically, one or two processor structures with roughly specified interconnection network will remain as a result of the data transfer analysis. These processors are implemented in detail by the cosynthesis. Again, the designer can check alternative solutions. This allows to investigate implementation details that were not evaluated by the more abstract analysis steps. The design tools help the designer because they facilitate the fast implementation of alternative designs.

These architectures can also be used as building blocks for the design flow. In principal, they are variations of Johnson's generic superscalar architecture [103]. They differ mainly in the names of the instructions and in the specific way of handling interrupts. Comparing the architectures to the VLIW template shows many similarities. The main difference is the instruction fetch. Superscalar processors require some form of reorder buffer and reservation stations. Synthesizing these components directly with a normal ASIC library would be too costly.

The first three functions in the example consume approximately 96% percent of the total operation count. A second important information concerns the different types of operations that are used. This is called the instruction mix. It can be used to adapt the number of functional units to the required number of operations. A third property is the change of the instruction mix when comparing different functions. The meT function, i_rev_dct, requires many additions, many compares, and many load/store opera- QUANTITATIVE ANALYSIS 49 tions.

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