Download Information Security Applications: 16th International by Ho-won Kim, Dooho Choi PDF

By Ho-won Kim, Dooho Choi

This booklet constitutes the completely refereed post-workshop complaints of the sixteenth overseas Workshop on info protection purposes, WISA 2015, hung on Jeju Island, Korea, in August 2015.

The 35 revised complete papers offered during this quantity have been rigorously reviewed and chosen from seventy eight submissions. The papers are prepared in topical sections equivalent to safeguard; cryptography, aspect channel assaults and countermeasures; defense and possibility research; IoT defense; community protection; cryptography; program security.

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Additional info for Information Security Applications: 16th International Workshop, WISA 2015, Jeju Island, Korea, August 20-22, 2015, Revised Selected Papers

Example text

This nice features are well suited on modern parallel computer architectures such as SIMD (Single Instruction Multiple Data). 3 times faster than other SHA-3 finalists over modern SIMD architectures. In this paper, we introduce the implementations of LSH hash functions for low-end embedded processors. The results show that LSH function are efficient enough to perform the operation over resource challenging processors so far. Keywords: Hash function tion · AVR · MSP · ARM 1 · ARX operations · Software implementa- Introduction In ICISC’14, a new hash function family named LSH was released [7].

After 1 The 32-bit wise inner loops are optimal choice because each instruction set occupies 2 bytes and 32-bit instruction only needs four consecutive instructions(8 bytes = 4×2) If we use 8-bit instruction as a minimum loop for 32-bit addition, we should use 1 ADD, 1 MOV, 1 INC, 1 CPSE and 1 RJMP and total 10 bytes with far slow performance. Compact Implementations of LEA Block Cipher 33 Fig. 2. Inner and outer loops of LEA encryption then, 24 times of round operations are iterated. Of the 26 registers, the 16 registers are assigned for plaintext and four registers for rotation counter, one for round counter and five for temporal registers.

The ATmega128 processor has RISC architecture with 32 registers. Of 32 registers, 6 registers (R26-R31) serve as the special pointers for indirect addressing. The remaining 26 registers are available for arithmetic operations. One arithmetic instruction incurs one clock cycle, and memory instructions or 8-bit multiplication incur two processing cycles. In Table 1, the detailed instructions used in this paper are drawn. 3 16-Bit Embedded Platform: MSP The MSP430 is a representative 16-bit processor board with a clock frequency of 8 MHz, 32–48 KB of flash memory, 10 KB of RAM, and 12 general purpose registers from R4 to R15 available [5].

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