Download Fully-Depleted SOI CMOS Circuits and Technology for by Takayasu Sakurai PDF

By Takayasu Sakurai

An important factor confronting CMOS expertise is the ability explosion of chips bobbing up from the scaling legislations. Fully-depleted (FD) SOI expertise offers a promising low-power strategy to chip implementation. Ultralow-power VLSIs, that have an influence intake of under 10 mW, might be key elements of terminals within the coming ubiquitous-IT society. Fully-Depleted SOI CMOS Circuits and expertise for Ultralow-Power functions addresses the matter of lowering the provision voltage of traditional circuits for ultralow-power operation and explains power-efficient MTCMOS circuit layout for FD-SOI units at a provide voltage of half V.

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Doken, and H. S. Devices Fabricated on Buried SiO2 Layers Formed by Oxygen Implantation into Silicon,” Electron. , Vol. 14, pp. 593-594, 1978. 8] T. Nishimura, Y. Inoue, K. Sugahara, S. Kusunoki, T. Kumamoto, S. Nakagawa, M. Nakaya, Y. Horiba, and Y. Akasaka, “Three Dimensional IC for High Performance Image Signal Processor,” IEDM Tech. Digest, pp. 111-114, 1987. 9] K. Kato, T. Wada, and K. Taniguchi, “Analysis of Kink Characteristics in Silicon-On-Insulator MOSFET’s Using Two-Carrier Modeling,” IEEE Trans.

E. Self-heating effects We have seen the beneficial effects that the buried insulating film underneath an SOI MOSFET has on the electrical characteristics. However, the thermal properties must also be considered. 4 Wm–1K–1, which is two orders of magnitude smaller than that of Si (140 Wm–1K–1). As a result, the Joule heat generated by the drain current cannot easily escape through the BOX and the substrate. 18]. A large amount of Joule heat is generated in the saturation region, where the drain voltage and current are both large; and the resulting increase in temperature reduces the drain current by lowering the carrier mobility, and 45 may lead to the appearance of a differential negative resistance in the drain current-voltage characteristics.

Shahidi, “Mainstreaming SOI Technology for High Performance CMOS,” Electrochemical Society Proceedings, Vol. 99-18, pp. 267-274, 1999. 2] N. Cohen, T. S. Sriram, N. Leland, D. Moyer, S. Butler, and R. Flatley, “Soft Error Considerations for Deep-Submicron CMOS Circuit Applications,” IEDM Tech. Digest, pp. 315-318, 1999. 3] H. Gotou, Y. Arimoto, M. Ozeki, and K. Imaoka, “Soft Error Rate of 64k SOI-DRAM,” IEDM Tech. Digest, pp. 870-871, 1987. 4] P. K. Weimer, “The TFT – A New Thin-Film Transistor,” Proceedings of IRE, Vol.

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