By Jörg Wilberg
Codesign for Real-Time Video Applications describes a contemporary layout method for embedded structures. It combines the layout of undefined, software program, and algorithms. often, those layout domain names are taken care of individually to minimize the layout complexity. complicated layout instruments help a codesign of the several domain names which opens a chance for exploiting synergetic results.
The layout method is illustrated via the layout of a video compression process. it truly is built-in into the video card of a computer. A VLIW processor structure is used because the foundation of the compression procedure and well known video compression algorithms (MPEG, JPEG, H.261) are analyzed. a whole top-down layout circulate is gifted and the layout instruments for every of the layout steps are defined.
The instruments are built-in into an HTML-based layout framework. The ensuing layout facts may be without delay built-in into the WWW. it is a the most important point for helping disbursed layout teams. The layout facts may be at once documented an go referencing in a virtually arbitrary method is supported. this offers a platform for info sharing one of the varied layout domain names.
Codesign for Real-Time Video Applications makes a speciality of the multi-disciplinary facets of embedded procedure layout. It combines layout automation and complex processor layout with a huge software area. A quantitative layout technique is emphasised which focuses the layout time at the most important elements. therefore permitting a quick and price effective layout method.
This publication should be of curiosity to researchers, designers and executives operating in embedded approach design.
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Again a reduction of the design space is achieved. Typically, one or two processor structures with roughly specified interconnection network will remain as a result of the data transfer analysis. These processors are implemented in detail by the cosynthesis. Again, the designer can check alternative solutions. This allows to investigate implementation details that were not evaluated by the more abstract analysis steps. The design tools help the designer because they facilitate the fast implementation of alternative designs.
These architectures can also be used as building blocks for the design flow. In principal, they are variations of Johnson's generic superscalar architecture . They differ mainly in the names of the instructions and in the specific way of handling interrupts. Comparing the architectures to the VLIW template shows many similarities. The main difference is the instruction fetch. Superscalar processors require some form of reorder buffer and reservation stations. Synthesizing these components directly with a normal ASIC library would be too costly.
The first three functions in the example consume approximately 96% percent of the total operation count. A second important information concerns the different types of operations that are used. This is called the instruction mix. It can be used to adapt the number of functional units to the required number of operations. A third property is the change of the instruction mix when comparing different functions. The meT function, i_rev_dct, requires many additions, many compares, and many load/store opera- QUANTITATIVE ANALYSIS 49 tions.